
PI74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
2
PS8133A
01/31/00
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Pin Name
Description
OE
Output Enable Input (Active HIGH)
LE
Latch Enable (Active HIGH)
CLK
Clock Input (Active HIGH)
Ax
Data I/O
Bx
Data I/O
GND
Ground
VCC
Power
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
25
26
27
28
32
31
30
29
Product Pin Description
Truth Table(1)
Notes:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑=LOW-to-HIGHTransition
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, CLKBA.
Output level before the indicated steady-state input
conditions were established, provided that CLKAB is HIGH
before LEAB goes LOW.
§ Output level before the indicated steady-state input
conditions were established.
Product Pin Configuration
56-PIN
V-56
A-56
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
s
t
u
p
n
I
B
t
u
p
t
u
O
B
A
E
OB
A
E
LB
A
K
L
CA
LX
X
Z
HH
X
L
HH
X
H
HL
↑
LL
HL
↑
HH
HL
H
X
B0
HL
L
X
§
0
B